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agwidera
public
iqs-timing
hardware
clock-trigger-board

C

clock-trigger-board

Project information

PCB to convert clock from 10 MHz sine to HSTL and provides a duplex trigger connection at 5 V TTL.

37 Commits
1 Branch
0 Tags

README

Created on

May 04, 2022

Copy SSH clone URLgit@gitlab.rlp.net:agwidera/public/iqs-timing/hardware/clock-trigger-board.git
Copy HTTPS clone URLhttps://gitlab.rlp.net/agwidera/public/iqs-timing/hardware/clock-trigger-board.git